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Cache memory
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551	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-04-04 17:00:54 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
552	Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors Marcelo Cintra Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:25:05 Computer architecture CPU cache Memory disambiguation Squash Branch predictor Parallel computing Central processing unit Monitor Speculative execution Computer memory Computing Computer hardware
553	An Exploration of L2 Cache Covert Channels in Virtualized Environments Kaustubh Joshi, Matti Hiltunen, Richard Schlichting Yunjing Xu, Michael Bailey, Add to Reading List Source URL: mdbailey.ece.illinois.edu Language: English - Date: 2014-08-05 13:28:17 Information theory CPU cache Cache Central processing unit Computer memory Amazon Elastic Compute Cloud Hyper-V Covert channel Channel Computing Computer architecture System software
554	Digital Semiconductor Alpha[removed]and Alpha 21064A Microprocessors Hardware Reference Manual Order Number: EC–Q9ZUC–TE Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:01:58 Computing Alpha 21064 Computer memory DEC Alpha PALcode CPU cache Instruction set Alpha 21164 Computer architecture Computer hardware Central processing unit
555	21264/EV68A Microprocessor Hardware Reference Manual Part Number: DS–0038B–TE This manual is directly derived from the internal[removed]EV68A Specifications, Revision 1.1. You can access this hardware reference manual Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:05 Instruction set architectures Computer memory DEC Alpha PALcode Alpha 21264 CPU cache ARM architecture Processor register Instruction set Computer architecture Computer hardware Central processing unit
556	Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors Marcelo Cintra, Jose´ F. Mart´ınez, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-C Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 12:21:04 Central processing unit Microprocessors CPU cache Cache Computer memory Parallel computing Microarchitecture Memory disambiguation Data structure alignment Computer hardware Computer architecture Computing
557	Compiler Writer’s Guide for the[removed]Part Number: EC–0100A–TE This document provides guidance for writing compilers for the[removed]and Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:16 Central processing unit Computer memory DEC Alpha Data structure alignment CPU cache Instruction set Floating point Classic RISC pipeline X86 Computer architecture Computing Instruction set architectures
558	The Design Complexity of Program Undo Support in a General-Purpose Processor Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 18:49:08 Central processing unit Cache CPU cache Computer memory Microarchitecture AMD 10h Parallel computing LEON Speculative execution Computer hardware Computer architecture Computer engineering
559	256 IEEE TRANSACTIONS ON COMPUTERS, VOL. 48, NO. 2, Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-04 15:57:37 CPU cache Cache Memory hierarchy Parallel computing Silicon Graphics Dynamic random-access memory Non-Uniform Memory Access Computer memory Computer hardware Computing
560	WeeFence: Toward Making Fences Free in TSO ∗ Yuelu Duan, † Abdullah Muzahid, Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-04-25 09:29:13 Computer memory Central processing unit Memory barrier CPU cache Write buffer Parallel computing Cache Compiler optimization Microarchitecture Computer architecture Computing Computer hardware

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